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document number: MC33902 rev. 3.0, 8/2009 freescale semiconductor advance information * this document contains certain information on a new product. specifications and information herein are subject to change without notice. ? freescale semiconductor, inc. , 2007-2009. all rights reserved. high speed can interface with embedded 5.0 v supply the MC33902 is a high speed can physical interface. the device includes an internal 5.0 v supply for the can bus transceiver, and requires only a connection to a battery line. the MC33902 provides 4 operation modes, including low power modes with remote and local wake-up. the device has very low sleep and standby current consumption. features ? high speed can interface for baud rates of 40 kb/s to 1.0 mb/s ? compatible to iso11898 standard ? single supply from battery. no need for a 5.0 v supply for can interface ? i/o compatible from 2.75 v to 5.5 v via a dedicated input terminal (3.3 v or 5.0 v logic compatible) ? low power mode with remote can wake-up and local wake-up recognition and reporting ? can bus failure diagnostics and txd/rxd pin monitoring, cold start detection, wake-up sources reported through the e rr pin ? enhanced diagnostics for bus, txd, rxd and supply pins available through pseudo spi via existing terminals en, stby and e rr . ? split terminal for bus recessive level stabilization ? inh output to control external voltage regulator ? pb-free packaging designated by suffix code ef figure 1. MC33902 simplified application diagram high speed can physical interface ef suffix (pb-free) 98asb42565b 14-pin soicn 33902 ordering information device temperature range (t a ) package mcz33902ef/r2 -40c to 125c 14 soic split vsup gnd inh wake mcu voltage i/o tx rx vdd can bus canl canh rxd stby en e rr txd can controller vdd 33902 v bat bus driver bus 5v reg inh vio 30 30 i/o & control diag. & receiver regulator
analog integrated circuit device data 2 freescale semiconductor 33902 internal block diagram internal block diagram figure 2. 33902 simplifi ed internal block diagram differential receiver driver driver 2.5 v receiver pattern detection vsup canh canl qh ql rin rin inh stby e rr v sup logic control / interface / p_spi vio 5.0 v regulator vdd failure detection buffer vdd split monitoring inh wake-up & management wake gnd detector control txd rxd en vio thermal
analog integrated circuit device data freescale semiconductor 3 33902 pin connections pin connections figure 3. 33902 pin connections table 1. 33902 pin definitions pin number pin name pin function formal name definition 1 txd input transmit data can bus transmit data input pin 2 gnd output ground ground termination 3 vdd output voltage digital drain can dedicated internal voltage regulat or, (decoupling capacitor required for voltage stabilization) 4 rxd output receive data can bus receive data output pin, wake-up flag in low power mode 5 vio input voltage supply for i/o input supply for the digital input output pins 6 en input enable enable input for devic e static mode control. mosi (master out, slave in) during p_spi operation. 7 inh output inhibit inhibit output for control of an external power supply regulator 8 e rr output active low error pin for static error and wake-up flag reporting miso (master in, slave out) during p_spi operation. 9 wake input wake wake input 10 vsup input voltage supply battery supply pin 11 split output split output for connection of the can bus termination middle point 12 canl input/output can low can low pin 13 canh input/output can high can high pin 14 stby input standby standby input for device static mode control. clk (clock) during p_spi operation. pin configuration 4 5 6 7 2 3 14 11 10 9 8 13 12 1 stby vsup wake e rr canh canl split txd vio en inh gnd vdd rxd
analog integrated circuit device data 4 freescale semiconductor 33902 electrical characteristics maximum ratings electrical characteristics maximum ratings table 2. maximum ratings all voltages are with respect to grou nd, unless otherwise noted. exceeding these ratings may cause a malfunction or permanent damage to the device. ratings symbol value unit electrical ratings dc voltage on vsup v sup -0.3 to +40 v dc voltage on canl, canh, split continuous (steady state) transient voltage (load dump) v bus -27 to +27 -27 to +40 v dc voltage on vio v vio -0.3 to 5.5 v dc voltage on en, stby , e rr , txd, rxd v dig -0.3 to vio +0.3 v dc voltage on wake v wake -0.3 to 29 v continuous current on canh and canl ilh 200 ma dc current on vdd ivdd 240 ma esd on canh, canl and split (hbm) v esdch +-2000 v esd on canh, canl and split (iec61000-4, c zap = 150 pf, rzap = 330 ) v esdiec +-8000 v esd on all pins except canh, canl, split (hbm) v esch +-2000 v thermal ratings junction temperature t j 150 c ambient temperature t a -40 to 125 c storage temperature t st -55 to 165 c thermal resistance thermal resistance junction to ambient (so14) r ja 140 c/w
analog integrated circuit device data freescale semiconductor 5 33902 electrical characteristics static electrical characteristics static electrical characteristics table 3. static electric al characteristics characteristics noted under conditions 5.5 v v sup 27 v, - 40 c t a 125 c, gnd = 0 v, unless otherwise noted. typical values noted reflect the approximate parameter means at t a = 25c under nominal conditions, unless otherwise noted. characteristic symbol min typ max unit input pin (vsup) nominal voltage range v supn 5.5 - 27 v extended voltage range, fully functional, parametric value(s) not guaranteed v supex 4.5 - 5.5 v supply current in sleep mode, v sup 13.5 v, vio = 0 v isup sleep - 10 a supply current in standby mode (v sup 13.5 v, 5 v enabled at vdd terminal, default operation) isup stb - 14 30 a supply current in normal mode, txd high isup normal 1.0 4.0 6.0 ma supply current in listen only mode, txd high isup listen 1.0 4.0 6.0 ma batfail flag internal threshold vbf ths 1.5 3.3 5.5 v batfail flag hysteresis vbf hys - 0.5 - v v sup under-voltage threshold (in normal and listen only) vsuv - 5.8 - v v sup under-voltage threshold hysteres is (in normal and listen only) vsuv hys - 0.2 - v output pin (vdd) output voltage vdd out 4.5 5.0 5.5 v drop voltage at i out = 100 ma v drop - - 500 mv vdd low detection threshold vdd th 4.0 4.25 4.5 v output current capability, for information only. current for can tranceiver supply only. i out 150 - - ma current source capability, in standby and go to sleep mode. i outlp 5.0 - 100 a thermal prewarning junction temperature (available via p_spi. e rr low if e rr -ext flag is set) t pr 130 150 170 c thermal shutdown (junction) t sd 155 170 190 c temperature threshold difference t diff 20 - - c external capacitor c ext 1.0 - 100 f input supply pin (vio) voltage range v io 2.75 ? 5.5 v input current in normal and listen only modes, rxd and e rr pin current =0, txd = high i violist 5.0 30 200 a input current in normal mode, txd = 0 v (normal and listen only) i vionorm 50 350 1000 a input current in standby or sleep mode, v io < 5.0 v i vioslp-stby ? 2.0 5.0 a
analog integrated circuit device data 6 freescale semiconductor 33902 electrical characteristics static electrical characteristics logic input pins (en, stby , txd) high level input voltage v ih 0.7 vio - - v low level input voltage v il - - 0.3 vio v pull-down current, en, stby , v in = v io i pd en- stby 1.0 4.0 10 a pull-up current, txd, v in = 0 v i pd txd - -250 - a data output pins (rxd) and ( err ) low level output voltage i = 5.0 ma vout low 0.0 - 0.3 vio v high level output voltage i = -3.0 ma vout high 0.7 vio - vio v high level output current v = vio - 0.4 v iout high -12 -5.0 -2.0 ma low level output current v = 0.4 v iout low 2.0 5.0 12 ma output pin (inh) output drop voltage (i inh) , i out = 100 ua) inh drop 0.05 0.2 0.8 v leakage current (sleep mode) inh leak - - 5.0 a input pin (wake) low level threshold voltage wake lth 2.0 2.5 3.0 v high level threshold voltage wake hth 2.0 2.7 3.5 v input current v wake = -0.2 to 18 v iwake in -10 0 10 a logic input/output pins (canh, canl) bus pins common mode voltage for full functionality v com -12 - 12 v differential input voltage, recessive state at rxd v canh-vcanl-r - - 500 mv differential input voltage, dominant state at rxd v canh-vcanl-d 900 - mv differential input hysteresis (rxd) v diff-hyst - 100 - mv input resistance r in 5.0 - 50 k differential input resistance r ind 10 - 100 k common mode input resistance matching r inm -3.0 0.0 3.0 % canh output voltage(45 < r bus < 65 ) tx dominant state tx recessive state v canh 2.75 2.0 3.5 2.5 4.5 3.0 v canl output voltage(45 < r bus < 65 ) tx dominant state tx recessive state v canl 0.5 2.0 1.5 2.5 2.25 3.0 v differential output voltage(45 < r bus < 65 ) tx dominant state tx recessive state v oh -v ol 1.5 -500 2.0 0.0 3.0 50 v mv table 3. static elec trical characteristics characteristics noted under conditions 5.5 v v sup 27 v, - 40 c t a 125 c, gnd = 0 v, unless otherwise noted. typical values noted reflect the approximate parameter means at t a = 25c under nominal conditions, unless otherwise noted. characteristic symbol min typ max unit
analog integrated circuit device data freescale semiconductor 7 33902 electrical characteristics static electrical characteristics logic input/output pins (canh, canl) (continued) canh output current capability - dominant state i canh - - -25 ma canl output current capability - dominant state i canl 25 - - ma canl over-current detection - error reported in register i canl-oc 75 120 195 ma canh over-current detection - error reported in register i canh-oc -195 -120 -75 ma canh, canl input resistance dev ice supplied and in sleep mode, vcanh, vcanl from 0 v to 5.0 v r insleep 5.0 - 50 k canl, canh output voltage in sleep and standby modes (45 < r bus < 65 ) v canlp -0.1 0.0 0.1 v canh, canl input current, device un supplied, v sup and v io connected to gnd (ref. fig.) vcanh, vcanl = 5.0 v vcanh, vcanl = -2.0 to + 7.0 v i can - - - - 250 400 a canh and canl diagnostic information canl to gnd detection threshold v lg - 1.75 - v canh to gnd detection threshold v hg - 1.75 - v canl to v bat detection threshold, valid if v sup > 7.0 v v lvb - v sup -2.0 - v canh to v bat detection threshold, valid if v sup > 7.0 v v hvb - v sup -2.0 - v canl to v dd detection threshold v l5 - v dd -0.43 - v canh to v dd detection threshold v h5 - v dd -0.43 - v split output voltage loaded condition i split =+- 500 a unloaded condition rmeasure > 1.0 m v split 0.3 v dd 0.45 v dd 0.5 v dd 0.5 v dd 0.7 v dd 0.55 v dd v leakage current -12 v < v split < +12 v -22 v < v split < +35 v i lsplit - - 0.0 - 5.0 70 a table 3. static elec trical characteristics characteristics noted under conditions 5.5 v v sup 27 v, - 40 c t a 125 c, gnd = 0 v, unless otherwise noted. typical values noted reflect the approximate parameter means at t a = 25c under nominal conditions, unless otherwise noted. characteristic symbol min typ max unit
analog integrated circuit device data 8 freescale semiconductor 33902 electrical characteristics dynamic electrical characteristics dynamic electrical characteristics table 4. dynamic electri cal characteristics characteristics noted under conditions 5.5 v v sup 27 v, - 40 c t a 125 c, gnd = 0 v, unless otherwise noted. typical values noted reflect the approximate parameter means at t a = 25c under nominal conditions, unless otherwise noted. characteristic symbol min typ max unit timing (ref to fig 7) txd dominant state timeout t dout 300 600 900 s bus dominant clamping detection t dom 300 700 1000 s propagation loop delay txd to rxd, recessive to dominant t lrd 60 140 210 ns propagation delay txd to can, recessive to dominant t trd - 70 110 ns propagation delay can to rxd, recessive to dominant t rrd - 45 140 ns propagation loop delay txd to rxd, dominant to recessive t ldr 50 120 200 ns propagation delay txd to can, dominant to recessive t tdr - 75 150 ns propagation delay can to rxd, dominant to recessive t rdr - 50 140 ns loop time txd to rxd, slew rate 1 (selected by p_spi) rec to dom dom to rec t loopsl1 50 - 310 ns loop time txd to rxd, slew rate 2 (selected by p_spi) rec to dom dom to rec t loopsl2 50 - 310 ns state machine timing external wake-up filter time t wake - 10 - s 3-pulse pattern wake-up - pulse width v diff = 1.15 v, ta =-40c v diff = 2.0 v, ta =-40c v diff = 1.15 v, 25c ta 125c. t pwidth 2.5 2.0 2.0 - - - - - - s time to report local wake-up event t loc wake- rep - 35 - s time to report can wake-up event t can wake- rep - 25 - s device state transition time (p_spi versus static mode change distinction) except from standby and go to sleep modes t dev-tr 8.0 - 15 s transition time from standby mode to any mode t lp-np - 35 - s transition time from go to sleep to sleep mode (?go to sleep? command) t h - 35 - s v io low to sleep mode timing t vio- slp - 10 - ms v dd low to can driver disable timing t vdd-canoff - 10 - ms v dd low to regulator disable timing t vddoff - 50 - ms pseudo spi (p_spi)timing p_spi operation frequency freq 0.0625 - 4.0 mhz sclk clock high time t wsclkh 0.125 - 8.0 s sclk clock low time t wsclkl 0.125 - 8.0 s en to falling edge of stby t sisu 40 - - ns falling edge of stby to en t sih 40 - - ns err rise time cl = 15 pf t rso - 25 50 ns err fall time cl = 15 pf t fso - 25 50 ns
analog integrated circuit device data freescale semiconductor 9 33902 electrical characteristics timing diagrams timing diagrams figure 4. p_spi timing figure 5. propagation loop delay txd to rxd time from rising edge of stby to err valid data t valid - - 50 ns delay between p_spi command and can in normal mode or can in sleep mode. device in normal mode (measured after p_spi 8th clock cycle rising edge). t canon-off - - 20 s table 4. dynamic elec trical characteristics characteristics noted under conditions 5.5 v v sup 27 v, - 40 c t a 125 c, gnd = 0 v, unless otherwise noted. typical values noted reflect the approximate parameter means at t a = 25c under nominal conditions, unless otherwise noted. characteristic symbol min typ max unit d7 dn d0 stby di7 en do7 e rr t valid t sisu t sih t wsclkh t wsclkl din di0 t pclk do0 do6 en and e rr state changed at stby rising edge txd rxd 0.3 v io t lrd 0.7 v io t ldr 0.3 v io 0.7 v io
analog integrated circuit device data 10 freescale semiconductor 33902 electrical characteristics timing diagrams figure 6. propagation delays txd to can and can to rxd figure 7. test circuit for timing characteristics txd v diff 0.3 v io 0.9 v t trd 0.7 v io 0.5v t tdr rxd t rrd t rdr 0.3 v io 0.7 v io vsup 12 v vio canl 33902 2.2 f 10 f split gnd txd rxd signal generator all pins are not shown r bus 15 pf c bus 100 pf 60 100 nf vdd canh en stby 5.0 v 100 nf 5.0 v
analog integrated circuit device data freescale semiconductor 11 33902 functional description functional pin description functional description functional pin description transmit data (txd) this input is the can transmit data pin. it is the interface from the mcu to the output on the can bus. if txd is low (dominant), then the signal on the can bus will be dominant (canh is ~5.0 v and canl is ~0 v). if txd is high (recessive), then the signal on the can bus will be recessive (canh and canl will be ~2.5 v). the txd thresholds are 3.3 v and 5.0 v compatible (depending on vio voltage) to accommodate the implementation of various mcus. there are three slew rates available, which are selected via the pseudo spi. ground (gnd) ground termination pin. voltage digital drain (vdd) this is the dedicated embedded supply voltage for the can interface. a capacitor must be connected to this pin. can interface current is sourced from this pin if device is in transmit and receive mode. in low power modes, current for the can interface is sourced directly from the vsup pin. receive data (rxd) this output pin is the can rece ive data. it is the interface to the mcu, which reports the state of the can bus. if the can bus is recessive (canh and canl ~2.5 v), then the signal on rxd will be high (recessive). if the can bus is dominant (canh is ~5.0 v and canl is ~0 v), then the signal on rxd will be low (dominant). this pin is also an active-low wake-up flag in low power, which reports a wake- up event to the mcu. rxd thresholds are 3.3 v and 5.0 v compatible (depending on the vio voltage) to accommodate the implementation of various mcus. voltage supply for i/o (vio) this is the dedicated input supply pin to determine voltage thresholds for the digital input/output pins. the vio thresholds range from 2.75 v to 5.5 v to accommodate the implementation of 3.3 v or 5.0 v mcus. enable (en) this is the enable input pin for device static mode control. this pin is connected to the m cu to place transceiver in the desired mode. functional voltage thresholds are determined by vio voltage to accommodate the implementation of 3.3 v or 5.0 v mcus. mosi (master out, slave in) during pseudo spi communication. inhibit (inh) the inhibit output pin controls an external power supply regulator. when the inh output is low, the external regulator is expected to shut down, which would then turn off the mcu and any other device that is powered up by the external regulator. this should consi derably decrease the module?s current consumption. active low error ( e rr ) the dedicated active low flag reporting pin reports any static errors, flags and wake-ups to the mcu depending on devices operating state. miso (master in, slave out) during pseudo spi communication. wake (wake) the wake input pin is used to wake-up the device from sleep mode after a battery to gnd, or gnd to battery transition. this pin is usually co nnected to an external switch in the application module, and sh ould not be left open. if wake pin functionality is not being used, it should be connected to gnd to avoid fals e wake-ups. this pin exhibits a high-impedance for low input current when implemented below 18 v. if voltage exceeds 18v at the pin, a series resistor should be used to limit the amount of current that the device will start sinking. voltage supply (vsup) this is the power supply input pin. the dc operating voltage for the device is 5.5 v to 27 v. a reverse battery protection diode should be implemented. this pin is able to sustain automotive transient conditions, such as 40 v load dumps and 27 v jump start conditions. the device?s quiescent sleep current is typically around 10 a. split (split) this is the output pin for middle point connection of canh and canl when implementing sp lit termination. pin voltage is typically around half of vdd (2.5 v) with or without loads. this pin must be left open if split can termination is not implemented. can high (canh) this is the can high input/outp ut pin. canh circuitry is design to work as a high side switch connected to vdd. in the recessive state, this switch is turned off and canh is then biased to split voltage or gnd, depending on device?s operating state. in the dominant st ate, the switch is turned on and canh is biased to vdd voltage. the canh pin is protected and diagnostics reporti ng is available against short to battery, gnd, and 5.0 v (vdd).
analog integrated circuit device data 12 freescale semiconductor 33902 functional description functional pin description can low (canl) this is the can low input/out put pin. canl circuitry is design to work as a low side switch connected to gnd. in the recessive state, this switch is turned off and canl is then biased to split voltage or gnd, depending on device?s operating state. in the dominant st ate, the switch is turned on and canl is biased to gnd voltage. the canl pin is protected and diagnostics reporti ng is available against short to battery, gnd, and 5.0 v (vdd). standby ( stby ) this is the standby input pin for device static mode control. this pin is connected to the m cu to place transceiver in the desired mode. functional voltage thresholds are determined by vio voltage to accommodate the implementation of 3.3 v or 5.0 v mcus. clk (clock) during pseudo spi communication.
analog integrated circuit device data freescale semiconductor 13 33902 functional device operation operational modes functional device operation operational modes state diagrams figure 8. state diagram notes 1. coming from standby mode 2. if v i/o is still switched on 3. coming from normal mode 4. if batfail flag and wake-up flag are cleared. an attempt to enter sleep mode without batfail and wake-up flag cleared has no effect 5. limited current capability, to maintain the capacitor at v dd charged. 6. a high level on inh will report a wake-up in sleep mode 7. after 4 txd pulses rising edge normal mode (stby 1, en 1) v dd on, inh on listen only ( stby 1, en 0) standby ( stby 0, en 0 ) (from any state if v i/o low, after t vio-slp , if v sup > v suv driver on; receiver on, split 2.5 v v dd on, inh on driver off; receiver on, split 2.5 v go to sleep ( stby 0, en 1 ) v dd on, inh on terminated to ground, split hz e rr report: wake-up sleep ( stby 0, en 0 ) terminated to ground, split hz e rr report: wake-up (2) terminated to ground, split hz e rr report: wake-up mode ( stby , en ) legend: (can, split) (e rr ) (4) t>t h ( v dd on, inh) if v io on (2) power down power up local or can wake-up (4) if v io on (2) stby 1 stby 1 stby 1 stby 0 stby 0 en 1 en 1 en 1 en 0 stby 1 en 1 stby 0 en 0 en 0 stbyb 0 en 1 stbyb 1 en 1 stby 1 en 0 stby 0 en 0 stby 1 en 0 and with v io > v io low threshold stby 1 en 1 and v io > v io low threshold automatic transition controlled transition v dd off, inh hz (6) v dd on (5) , inh on err report: batfail ) (1) (v dd low, local failure) (3) err report: wake-up source & (v dd low and can bus failure) (7)
analog integrated circuit device data 14 freescale semiconductor 33902 functional device operation operational modes figure 9. v dd low illustration table 5. functional table stby en mode v dd inh rxd can err (active low) 0 0 standby on (8) high active low: report wake-up event (9) terminated to gnd active low: report wake-up event (9) 0 0 sleep off hz 0 1 go to sleep on high 1 0 listen only on high high: recessive state low: dominant state receiver: on driver: off ?report local failure, v dd low, bat fail 1 1 normal on high driver and receiver: on ?wake-up source (10) ?bus failures, v dd low notes 8. with limited current capability, in order to maintain the capacitor at v dd pin charged 9. provided if v io > 2.5 v. 10. before 4th tx pulse rising edge v sup ~3.0 v 5.0 v 5.0 v v dd v dd _low can driver disabled 10 ms e rr (1) 4.25 v 5.0 v v dd v dd _low can driver disable 10 ms e rr (1) 4.25 v v dd disabled 50 ms normal or listen only normal or listen only 2 v dd overload condition start end can driver enabled v dd re-enabled mode v dd low illustration, v sup > v sup low (v sup > 5.8 v) v dd low illustration, cranking pulse v sup < v sup low (v sup < 5.8 v) and crank bit low in p_spi register. en, stby , v io high 4.25 v 4.25 v 1) see figure on err reporting 2) v dd is re enabled when v sup recovers (v sup low flag goes from h to l) or by a mode change via en and stby input. v dd re-enabled (2) v dd disabled (3) 50 ms v sup _low 5.8 v v sup _low 5.8 v 3) capacitor charged maintained by internal device current source (3)
analog integrated circuit device data freescale semiconductor 15 33902 functional device operation operational modes device state description standby mode standby mode is a reduced current consumption mode. canh and canl lines are terminated to gnd, the split pin is high-impedance. in order to monitor bus activities, the can wake-up receiver is on, inh output remains on. the voltage on vio should be maintained. the vdd regulator is on with limited current capability, in order to maintain the capacitor at vdd charged and allow a fast transition to normal mode and fast can communication. wake-up events occurring on the can bus or on the wake pin are reported by a low level of the err and rxd pins. the standby mode is also the first mode entered after a device power up. in this case, the vdd regulator is activated to charge the v dd capacitor, and then th e regulator enters the reduced current capability mode, in order to optimize and reduce system current cons umption. depe nding upon the v dd capacitor ?s equivalent series resistance (esr), a voltage drop can be observed. see figure 10 . figure 10. v dd regulator start-up normal mode in normal mode, both the can driver and receiver are on. in this mode, the can bus is controlled by the txd pin level, and the can bus state is reported on the rxd pin. the vdd regulator is on. it supplies the can driver and receiver.the split pin is active and a 2.5 v biasing is provided on the split output pin. in normal mode, the err pin reports the wake-up source and the bus failure, after 4 txd pulses. normal mode is entered by setting the en and stby pins high. entering normal mode will clear the batfail flag. listen only mode this mode is used to disable the can driver, but leave the can receiver active. in this mode, the device is only able to report the can state on the rxd pin. the txd pin has no effect on can bus lines. this mode is entered by setting the en and stby pins to [0, 1]. in this mode, coming from normal mode, the err pin reports local failures occurring on the txd and rxd pins, and v dd low. when this mode is en tered from the standby mode, the err pin reports the batfail flag. the vdd regulator is on. the split pin is active and a 2.5 v biasing is provided on the split output pin. go to sleep mode go to sleep is an intermediate mode to ultimately set the device in sleep mode. the go to sleep is entered by setting the en and stby pins to [1, 0]. if the en and stby pins are maintained to [1,0] for a time longer than t h , the sleep mode is automatically entered. in go to sleep mode, the vdd regulator remains in its previo us state and the split pin is deactivated. inh is active. sleep mode the sleep mode is a low power mode. it is entered from the go to sleep mode by setting the en and stby pins to [1 0], and automatically from go to sleep mode after t h . in sleep mode, the vdd regulator is turned off and the split pin is deactivated, inh is high-impedance. in sleep mode and go to sleep mode, the device is able to wake-up on can bus activity or transitions on the wake pin. a wake-up from sleep mode will set the device in standby mode. sleep mode is also automatically reached if the voltage at vio is below the vio th for more time than t vio-slp . device main flags description: this section describes the flags available when the device is controlled via the en and stby pins in a static manner (no p_spi control). additional information and control are possible using the pseudo spi (refer to extended device operation ). batfail this flag is set to signal that the voltage on the vsup pin has dropped below vbf ths , particularly after the device was disconnected from the battery. in listen only mode, the batfail flag will be available on the err pin, coming from standby, go to sleep and sleep modes. when v sup is below vbf threshold, all internal flags and registers are reset to their initial condition. can bus wake-up (wu) from standby or sleep mode, th is flag is set if a correct pattern has been received on the can bus. this wake-up is reported on err and rxd pins by a low level in standby mode, as well as in sleep mode if vio is present. v dd low (4.25 v) 5v en, stby v e = esr x v dd current limitation v e v e v e wake-up event detected device start-up 0v standby normal sleep main v dd weak regulator on on main v dd on main regulator off
analog integrated circuit device data 16 freescale semiconductor 33902 functional device operation operational modes the flag is cleared by leaving the normal mode or by a p_spi reading. wake pin - local wake-up (wu) from the standby, go to sleep or sleep mode, this flag is set if a transition on the wake pi n is detected. this wake-up is reported on the err pin by a low level in standby mode, as well as in sleep mode if vio is present. the wake-up flag is cleared by leaving the normal mode or by p_spi reading. wake-up source wake-up source is reported on the err pin by entering normal mode, before 4 tx pulses. the err pin is low to indicate a local wake-up, and high to indicate can wake-up. local failure this flag is a logic ?or? of the following failures: txd dominant clamping, rxd recessive clamping, txd-to-rxd short-circuit and vdd low condition. this flag is reported in listen only on the err pin coming from normal mode. using the p_spi, it is possible to get detailed failure information. bus failure the bus failure flag is set if the can transceiver detects a bus line short-circuit condition to vsup, vdd, or gnd, during five consecutive domi nant-recessive cycles on the txd pin. in addition, this flag reports a bus dominant clamping condition. in normal mode, the bus failure flag is available on the err pin. using the p_spi, it is possible to get detailed failure information. vdd low v dd low flag is set in normal and listen only mode when v dd is below the v dd low threshold. after a time longer than t vdd-canoff , the can is disabled and after a time longer than t vddoff , the v dd regulator is disabled to avoid a battery discharge. if the crank bit is set high, the v dd regulator and can will not be disabled if v sup is below v suv . when v sup is above v suv , the crank bit has no effect. v dd low flag is reported in normal and listen only mode, so the user can differentiate between local and bus failures by changing modes and observing err staying low. in case of a double failure (local and bus failure) at the same time, the results will be the same: err low in normal and in listen only mode. however, this is unlikely to occur. this flag is cleared when entering low power, or when v dd is above v dd low threshold, plus the p_spi reading. the v dd regulator is re enabled as soon as v sup rises above v sup low, or by a mode change (refer to the crank pulse illustration). the can is re-enabled as soon as v dd is above v dd low threshold. (refer to cr ank pulse illustration). err pin the err pin reports various information depending upon the device state, the device st ate transition, and event on the txd pin. table 6 shows the diagnostic flag availability when the device is controlled in a static manner. table 6. ?static? diagnostic flags flag accessibility clearing diagnostic batfail listen-only mode (coming from standby, go-to-sleep, sleep) leaving normal mode canwu or local wu standby, go-to-sleep, sleep (provided vio is present) leaving normal mode or by setting the batfail wake-up source normal mode (before the fourth dominant to recessive edge on the txd pin) leaving normal mode, or by setting batfail flag. bus failure normal mode (after the fourth dominant to recessive edge on the txd pin) re-entering normal mode local failure listen only mode (coming from normal mode) entering normal mode or txd high while rxd low. v dd low normal mode (after the fourth dominant to recessive edge on the txd pin) and listen only mode (coming from normal mode) v dd > v dd low threshold evaluation mode by rxd low, when coming from sleep or standby into normal or listen only modes. rxd goes from low to high, to signal the device is ready and has exited low power modes (tlp-np parameter).
analog integrated circuit device data freescale semiconductor 17 33902 functional device operation operational modes figure 11 shows the meaning of the err pin versus the device state, the st ate transition and the events on txd. figure 11. err versus device state can interface description: can interface supply the supply voltage for the can driver is the vdd pin. the can interface also has a supply path from the battery line, through the vsup pin. this path is used in can sleep mode to allow wake-up detection. during can communication (transmission and reception), the can interface current is sourced from the vdd pin. during can low power mode, the current is sourced from the vsup pin. can driver operation in normal mode the can driver will be enabled as soon as the device is in normal mode and the txd pin is recessive. when the can interface is in normal mode, the driver has two states: recessive or dominant. the driver state is controlled by the txd pin. the bus state is reported through the rxd pin. when txd is high, the driver is set in the recessive state, and canh and canl lines are biased to the voltage set at vdd divided by 2, approx. 2.5 v. when txd is low, the bus is set into the dominant state, and the canl and canh drivers are active. canl is pulled low and canh is pulled high. the rxd pin reports the bus state: canh minus the canl voltage is compared versus an internal threshold (a few hundred mv). if ?canh minus canl? is below the threshold, the bus is recessive and rxd is set high. if ?canh minus canl? is above the threshold, the bus is dominant and rxd is set low. the split pin is active and provide a 2.5 v biasing to the split output. normal mode and slew rate selection the can signal slew rate se lection is done via the p_spi. by default, and if no p_spi is used, the device is in the fastest slew rate. three slew rates are available. the slew rate controls the recessive to dominant and dominant to recessive transitions, which are also dependent on canh and canl capacitance. this also affects the delay time from the txd pin to the bus, and from the bus to rxd. the loop time is thus affected by the sl ew rate selection. minimum baud rate the minimum baud rate is determined by the shortest txd permanent dominant timing detection. the maximum number of consecutive dominant bits in a frame is 12 (6 bits of active error flag and its echo error flag). the shortest txd dominant detection time of 300 s leads to a single bit time of: 300 s / 12 = 25 s. so the minimum baud rate is 1 / 25 s = 40 kbaud. wake-up event can wake-up or local wake-up => err low local failure vdd low, txd-pd, rxd-pr, txd short to rxd => e rr low batfail bus failure, vddlow, bus dom, 4 dominant wake-up source local wake-up => e rr low; can wake-up => e rr high go to sleep standby sleep 5.0 v or v bat => e rr low listen only normal stby = 0 en = x stby = 1 en = 0 stby = 1 en = 1 stby = 0 en = x stby = 0 en = x stby = 0 en = x pulses at txd stby = 1 en = 0 stby = 1 en = 1 stby = 1 en = 1 stby = 1 en = 0 device mode e rr meaning stby = 1 en = 1 stby = 1 en = 0 stby = 0 en = x canh or canl short to gnd v sup low => err high
analog integrated circuit device data 18 freescale semiconductor 33902 functional device operation operational modes termination the device supports the two main types of bus terminations: ? differential termination resistors between canh and canl lines ? split termination concept, with the mid point of the differen - tial termination connected to gnd through a capacitor, and to the split pin ? refer to typical application and bus termination options and wake pin configuration on page 27 low power mode in low power mode, the can is internally supplied from the vsup pin. in low power mode, the canh and canl drivers are disabled, and the receiver is also disabled. canh and canl have a typical 40 k impedance to gnd. the wake-up receiver can be activated if wake-up is enabled by the p_spi command. the split pin is high-impedance. when the device is set back into normal mode, canh and canl are set back into the recessive level. this is illustrated in the following diagram. . figure 12. bus signal in normal and low power mode wake-up when the can interface is in sleep mode with wake-up enabled, the can bus traffic is detected. the can bus wake- up signal is a pattern wake-up. can wake-up cannot be disabled. can wake-up report the can wake reports depend upon the low power mode selected, sleep or standby. in sleep mode, the inh pin is activated. in standby mode, the vio voltage is present and the wake-up is reported by the err and rxd pin low level. ref to table 5 . pattern wake-up in order to wake-up the can interface, the wake-up receiver must receive a series of 3 consecutive valid dominant pulses. this is the def ault setting in which the can wu-pattern bit is set low. can wu-pattern bit can be set high by p_spi, and the wake up will occur after a single pulse duration of a minimum of 4.0 s. a valid dominant pulse should be longer than t pwidth . the 3 pulses should occur in a time frame of 120 s to be considered valid. when 3 pulses pass these criteria the wake signal is detected. this is illustrated in figure 13 . . figure 13. pattern wake-up canl canh txd rxd 2.5 v canl-dom canh-dom canl/canh-rec 2.5 v high ohmic t termination (50kohms) to gnd split dominant state recessive state MC33902: bus driver MC33902: receiver (bus dominant set by other ic) high-impedance normal or listen only mode normal or listen only mode go to sleep, canh-canl sleep or standby mode incoming can message canl canh internal wake-up signal min t pwidth dominant internal differential wake-up receiver signal max 120 s can bus pulse # 1 dominant pulse # 2 dominant pulse # 3 dominant pulse # 4
analog integrated circuit device data freescale semiconductor 19 33902 functional device operation operational modes can bus diagnostic the aim is to implement a diagnostic of bus short-circuit to gnd, vbat, and the internal a pplication circ uit board 5.0 v. several comparators are implemented on the canh and canl lines. these comparators monitor the bus level in the recessive and dominant states. the information is then managed by the logic circuitry to properly determine the failure and report it. figure 14. can bus simpli fied structure truth tabl e for failure detection table 7 indicates the state of the comparators in case of a bus failure, and depend ing upon the driver state. detection principle in the recessive state, if one of the two bus lines are shorted to gnd, vdd, or vbat, the voltage at the other line follows the shorted line, due to the bus termination resistance. for example: if ca nl is shorted to gnd, the canl voltage is zero, the canh voltage measured by the hg comparator is also close to zero. in the recessive state, the failure detection to gnd or vbat is possible. however, it is not possible with the above implementation to distinguish which of the canl or canh lines are shorted to gnd or vbat. a complete diagnostic is possible once the driver is turned on, and in the dominant state. number of samples for proper failure detection the failure detector requires at least one cycle of the recessive and dominant states to properly recognize the bus failure. the error will be fully de tected after 5 cycles of the recessive-dominant states. as long as the failure detection circuitry has not detected the same error for 5 recessive- dominant cycles, the e rror is not reported. bus clamping detection if the bus is detected to be in dominant for a time longer than (t dom ), the bus failure flag is set and the err is set low in normal mode. such conditions could occur if the canh line is shorted to a high voltage. in this case, current will flow from the high voltage short-circuit through the bus termination resistors (60 ) and then in the split terminal (if used), and through the device canh and canl input resistors, which are terminated to an internal 2.5 v biasing or to gnd (sleep mode). depending upon the high voltage short-circuit, the number of nodes, usage of split terminal, r in actual resistor, and node state (sleep or active), t he voltage developed across the bus termination can be sufficient to create a positive dominant voltage between canh and canl. the rxd pin will be low. this would prevent the start of any can table 7. failure detection truth table failure description driver recessive state driver dominant state lg (threshold 1.75 v) hg (threshold 1.75 v) lg (threshold 1.75 v) hg (threshold 1.75 v) no failure 1 1 0 1 canl to gnd 0 0 0 1 canh to gnd 0 0 0 0 lb (threshold v sup -2.0 v) hb (threshold v sup -2.0 v) lb (threshold v sup -2.0 v) hb (threshold v sup -2.0 v) no failure 0 0 0 0 canl to vbat 1 1 1 1 canh to vbat 1 1 0 1 l5 (threshold v dd -0.43 v) h5 (threshold v dd -0.43 v) l5 (threshold v dd -0.43 v) h5 (threshold v dd -0.43 v) no failure 0 0 0 0 canl to 5.0 v 1 1 1 1 canh to 5.0 v 1 1 0 1 hg canh canl lg v dd v rg v rg hb v rvb lb v rvb logic tx diag v dd (5.0 v) gnd (0.0 v) recessive level (2.5 v) v bat (12-14 v) v rvb (v sup -2.0 v) v rg (1.75 v) canl dominant level (1.4 v) canh dominant level (3.6 v) l5 v r5 h5 v r5 v r5 (v dd -.43 v)
analog integrated circuit device data 20 freescale semiconductor 33902 functional device operation operational modes communication, and thus a proper failure identification (requires 5 pulses on txd). the bus dominant clamp circuit will help to determine such failure situation. rx permanent recessive failure the aim of this detection is to diagnose an external hardware failure at the rx ou tput pin and ensure that a permanent failure at rx d oes not disturb the network communication. if rx is shorted to a logic high signal, the can protocol module within the mcu will not recognize any incoming message. in addition it will not be able to easily distinguish the bus idle state and can start communication at any time. in order to prevent this, an rx failure detection is necessary. figure 15. rx path simplifi ed schematic, rx short to v dd detection implementation for detection the proposed implementation is to sense the rxd output voltage at each low to high transition of the differential receiver. excluding the internal propagation delay, the rxd output should be low when the diffe rential receiver is low. in case of an external short to vdd at the rxd output, rxd will be tied to a high level and can be detected at the next low to high transition of the differential receiver. as soon as the rxd permanent recessive is detected, the rxd driver is deactivated. once the error is detected, the flag is latched and the driver is disabled. the error is reported at err pin and via p_spi. recovery condition the internal recovery is done by sampling a correct low level at the bus as shown in figure 16 . figure 16. rx path simplified sche matic, rx short to v dd detection canh canl diff v dd rxsense rx driver rxd txd tx driver 60 v io logic diag canl&h diff output rxd output rx short to v dd prop delay rx flag rx flag latched v io/2 sampling sampling the rx flag is not the rxpr bit in the lpc regist er, and neither is the canf in the intr register. canl&h diff output rxd output rx short to v dd rx flag (internal signal) rx flag latched sampling sampling rx no longer shorted to v dd
analog integrated circuit device data freescale semiconductor 21 33902 functional device operation operational modes important informati on for bus driver reactivation rxd the driver stays disabled until the failure is cleared (rx is no longer permanent recessive). one transition on the can bus (internal differential rece iver transition), and the bus driver is activated by entering into normal mode. txd permanent dominant principle if the txd is set to a permanent low level, the can bus is set into dominant level, and no communication is possible. the 33902 has a txd permanent time out detector. after the timeout, the bus driver is disabled and the bus is released into a recessive state. the txd permanent flag is set. recovery the txd permanent dominant is used and activated in case of a txd short to rxd. the recovery condition for a txd permanent dominant (recovery means the re-activation of the can drivers) is done by entering into a normal mode controlled by the mcu, or when txd is recessive, while rxd changes from recessive to dominant. txd to rxd short circuit: principle if txd is shorted to rxd during incoming dominant information, rxd is set low. consequently, the txd pin is low and drives canh and canl into a dominant state. thus the bus is stuck in dominant state. no further communication is possible. detection and recovery the txd permanent dominant ti me out will be activated and release the canl and canh drivers. however, at the next incoming dominant bit, the bus will then be stuck in dominant again. the recovery condition is same as the txd dominant failure. extended device operation the device has extended func tionality which allows device control and diagnostic readings via the p_spi (pseudo serial peripheral interface), and using the stby , en and err pins. p_spi operation the p_spi operation is similar to a standard spi interface operation in slave mode. it uses the en, stby and err pins, which have the functions of mosi, sclk and miso. there is no chip select (cs). in write mode, the following functions and control are accessible: - can driver slew rate selection - err pin operation mode - can wake-up mode - crank mode operation in read mode, the following flags are available: - can bus detail diagnostic - local failure diagnostic - voltage monitoring - wake-up flags, wake pin level - p_spi errors - device identification p_spi diagram figure 17 illustrates the p_spi operation. a clock signal should be generated on the stby pin, en input operates as data in (mosi) and the err output pin operates as data out (miso). in order to start a p_spi operation, the level at stby should be low (1), as shown in figure 17 . bit d7 starts at the rising edge of stby . bit d7 level should be opposite to the level before. d7 is then internally sampled at the stby falling edge. the sampling of opposite level at (1) and (3) is the confirmation of a p_spi message start. then the p_spi bit d6 starts, and the device will drive the err pin to a level opposite to the one when p_spi started (5): this is the confirmation that the device has correctly detected a p_spi message start (acknowledgement). figure 17. : p_spi message start full p_spi message: figure 4 describes the complete p_spi message and timing. (1) (2) (3) stby en en d7 en en device in normal mode (4) d6 e rr err err err pin high at err pin low at err adr en=1 en=0 p_spi start p_spi start device in listen only adr (5) p_spi msg start p_spi msg detected (=acknowledge)
analog integrated circuit device data 22 freescale semiconductor 33902 functional device operation operational modes distinction between p_spi and traditional operation. the distinction between static device control and control via p_spi is performed by the duration of the en and stby level. if the en and stby levels change before a time of ?t dev-tr ? then the device detects a p_spi operation. if the en and / or stby levels are stable for a time longer than 15 s, then the device state will be changed according to en / stby level and device state diagram. this means that the device mode change is done after a delay of typ t dev-tr and consequently the p_spi frequency operation should be faster than (1 / (2 * t dev-tr ). with t dev-tr = 8.0 s, the spi equivalent frequency should be greater than 62.5 khz. end of p_spi message: at the p_spi message, the state of en and stby pins should be in line with the device mode expectation: example: if the device is in normal mode and should stay in normal mode after the p_spi command, the en and stby pins should be 1,1 at end of the p_spi command. if the device is in listen only mode, en and stby pins should be 0,1, in order to set or maintain the device in listen only mode. time between 2 p_spi message: a min delay of 15 s should be observed between two p_spi messages. the delay is measured between the last transition of the en/ stby of the 1st message, and the 1st en/ stby transition of the next message. p_spi avai lability: the p_spi is operating only in normal and listen only mode. it is not operating in standby and sleep modes. table 8 is the mapping of the p_spi register. low power mode definition: standby, go to sleep and sleep modes. table 8. p_spi bit mapping d7 d6 d5 d4 d3 d2 d1 d0 mosi star t adrr rb/w mosi 4 mosi 3 mosi 2 mosi 1 mosi 0 miso err ack=er rb miso 5 miso 4 miso 3 miso 2 miso 1 miso 0 mosi star t 0 0 (read) 0 1 0 1 0 1 0 1 0 1 miso err ack=er rb 0 batfa il x lxwu wils canw u test/ def vmonf spierr canf 0 mosi star t 0 1 (write) err _ext can sr1 can sr0 can wu - pattern crank miso err ack=er rb 0 0 pass id1 pass id0 met id1 met id0 mosi star t 1 0 1 0 1 0 1 0 1 0 1 0 1 miso err ack=er rb bus dom vdd temp rx-pr can cur tx-pd vso v canf2 vsuv canf1 vio low canf0 vddlo w batfail description v sup voltage < v sup low threshold, also called power on flag set v sup below v bfth (3.3 v) reset entering normal mode or p_spi reading (listen only) action avoid entering go to sleep. set err low in listen only mode coming from low power modes
analog integrated circuit device data freescale semiconductor 23 33902 functional device operation operational modes lxwu description wake-up event occurred on the wake pin set in low power mode, by a local wake pin transition reset exit normal mode or p_spi readi ng (listen only and normal mode) action avoid entering go to sleep mode. set err low in low power modes canwu description wake-up event occurred on can bus set in low power mode, by can wake-up reset exit normal mode or p_spi readi ng (listen only and normal mode) action avoid entering go to sleep mode. set err and rxd low in low power modes vmonf description voltage monitoring flag: or of v sov , v suv , v io , v ddlow , v dd prewarning temp set in normal and listen only modes: or of v sov , v suv , v io , v ddlow , v dd prewarning temp reset entering low power mode or (failure removed + p_spi reading (listen only and normal mode)) action if err _ext is set, err pin set low. err is low for the vdd low flag, despite the err -ext bit. canf description failure on the can bus. or of canf2, canf1, canf0 bits set in normal and listen only modes: or of txdpd, rxdpr, cancur, can bus failures reset entering low power mode or (failure removed + p_spi reading (listen only and normal mode)) action depending upon failure. ref to detail flag description wils description real time wake input level. low is wake belo w threshold, high is wake above threshold. set wake pin higher than threshold reset wake pin lower than threshold action no action spierr description pseudo spi error: incomplete transmission error during start of p_spi set when p_spi frame does not have 8 clock pulses reset entering low power mode or p_spi reading (listen only and normal mode) action p_spi wrong command is ignored err _ext description err pin operation report all flags configure by p_spi reset entering low power mode action when high, extend the err output pin to report all flags (when available) in any modes. when low (default) err reports default flags.
analog integrated circuit device data 24 freescale semiconductor 33902 functional device operation operational modes cansr (1,0) description 00: can slew rate 0 11: can slew rate 0 01: can slew rate 1 10: can slew rate 2 configure by p_spi in listen only and normal mode reset entering low power mode action change can slew rate (ref to parametric). default is 00. can wu - pattern description select between 2 wake-up mechanisms configure by p_spi in listen only and normal mode reset leaving low power mode action when high wake-up occurs after 1 pulse of a minimum of 4.0 s (parameter). when low, (default) wake- up occurs after 3 pulses of a minimum of 600ns (parameters). crank description when this flag is set, the v dd low condition does not disable can and v dd regulator, if v suv flag is set. configure by p_spi in normal and listen only modes reset entering low power mode or p_spi write (listen only and normal mode) action no disable of can and v dd regulator in case of a v dd low condition, and the v suv flag is set. err reports a v dd low condition. the p_spi vdd low flag is set. pass id(1,0), metid(1,0) set report device internal identification reset action bus dom description detect a bus voltage dominant for a time longer than t dom . set this flag is set if the bus is detected to be in dominant for more than t dom reset entering low power mode, bus recessive p_spi reading (listen only and normal mode) action no action, set err low in normal mode can cur description over-current occurred on the canh or canl driver set in normal mode, if the canh or canl current exceed the threshold (parameter) reset entering low power mode, the can current below th reshold + p_spi reading (listen only and normal mode) action by default no action. if the err -ext bit is set, the err is set low.
analog integrated circuit device data freescale semiconductor 25 33902 functional device operation operational modes rx-pr description rxd short to high (recessive level) set in normal and listen only modes, if the rx d permanent recessive c ondition is detected reset entering low power mode, the rxd recovery condition reached + p_spi reading (listen only and normal mode) action set the local failure flag, disable the can driver, set err low in listen only mode coming from normal mode tx-pd description txd permanent dominant set in normal modes, if txd permanent dominant condition detected reset entering low power mode, txd recovery condition reached + p_spi reading (listen only and normal mode) action set the local failure flag, disable the can driver, set err low in listen only mode coming from normal mode canf (2,1,0) description 0 0 0: no can bus failure 0 0 1:canl short to gnd 0 1 0: canl short to vdd 0 1 1: canl short to vbat 1 0 1: canh short to gnd 1 1 0: canh short to vdd 1 1 1: canh short to v sup set in normal modes, if can failure condition detected reset entering low power mode, can failure recovery condition reached + p_spi reading (listen only and normal mode) action set the bus failure flag, set the err low in normal mode after 4 tx pulses vdd temp description v dd regulator reaches temperature prewarning set in normal mode or listen only mode, if the v dd temperature reaches the prewarning threshold reset real time report, reset if the temperature falls below the prewarning threshold action by default no action. if the err -ext bit is set, err is set low. v sov description v sup over-voltage detected set in normal and listen only modes, if the v sup over-voltage threshold condition detected reset entering low power mode, v sup over-voltage threshold condition reco vered + p_spi reading (listen only and normal mode) action by default no action. if the err -ext bit is set, the err is set low.
analog integrated circuit device data 26 freescale semiconductor 33902 functional device operation operational modes v suv description v sup under-voltage detected set in normal and listen only modes, if the v sup under-voltage threshold condition detected reset entering low power mode, v sup under-voltage threshold condition re covered + p_spi reading (listen only and normal mode) action when v sup voltage rises above the v sus threshold, the v dd regulator is re-enabled if disabled previously by a v dd low condition v io low description v io low detected set in all modes, if v io under-voltage threshold condition detected reset entering low power mode, v io under-voltage threshold condition reco vered + p_spi reading (listen only and normal mode) action after 10ms, set the device in sleep mode, if v suv low (don?t enter sleep mode during crank and power up phase). v dd low description v dd voltage < v ddlow flag threshold set in all modes, if v dd under-voltage threshold condition detected reset entering low power mode, v dd under-voltage threshold condition reco vered + p_spi reading (listen only and normal mode), mode change between normal and listen only if v dd regulator was turned off previously by a v dd low condition for more than 50ms. action after 10 ms, disable the can, after 50 ms disable the regulator, if cr ank bit is set low (default).
analog integrated circuit device data freescale semiconductor 27 33902 typical applications typical applications figure 18. typical application and bus termination options and wake pin configuration inh stby e rr vio gnd txd rxd en micro vreg gpio rx tx v cc controller can controller v bat e n c1 d1 2.75 v to 5.0 v protocol c2 c3 canh canl split vdd c4 c5 c6 can bus 30 30 component list: d1: 1n4004 type c1: >=100 nf c2: >=100 nf c3: >=2.2 f c4: >=50 pf c5:>=50 pf c6: 1.0 to 10 nf c7: 1.0 to 63 f r1: 22 k rb: customer defined, ex 10 k vsup MC33902 v in v out gnd c4 r1 s wake c4 r1 s wake v bat rb switch to gnd switch to v bat wake unused wake canh canl split c4 c5 c6 can bus 30 30 split termination standard termination canh canl split c4 c5 can bus 60 no connect canh canl split c4 c5 can bus no termination no connect supported can terminations ecu connector MC33902: wake pin configurations rb v bat typical application c4 r1 s wake rb v bat c7
analog integrated circuit device data 28 freescale semiconductor 33902 comparison with competition 14 pin high speed can trans- ceiver comparison with competition 14 pin high speed can transceiver the table below is a comparison between the MC33902 and the competition 14 pin high speed can transceiver having no embedded power supply. item MC33902 competition w/o embedded regulator v dd pin output. requires local decoupling capacitor(s). no extra load should be connected. input. requires connection to a 5.0 v supply. wake pin fixed threshold typ 3.0 v with hysteresis. no pull-up or pull-down. high-impedance input. connect to gnd when not used. threshold v bat -3.0 v. active pull-up when input is above threshold. active pull-down wh en input is below threshold. err pin active low, reports flags, or used as miso during p_spi communication. strong driver (capability typ. 3.0 ma). active low, reports flags, weak driver, requiring 8.0 s stabilization time en and stby pins input used for static mode control. used as clock and mosi during p_spi communication. input used for mode control. bus dom failure flag failure reported on err pin in normal mode (considered as a bus failure => reported in normal mode) failure reported on the err pin in listen only mode (considered as a local failure) v dd low flag no effect on device mode. failure on can transceiver supply should not affect the complete ecu. v dd is disabled ?locally? to reduce current consumption. the err pin is set low in normal and listen only mode. v dd low threshold set at 4.25 v set the device into sleep mode. inh is turned off. if the ecu regulator is controlled by inh, ecu is turned off. v io low flag same same wake-up time from sleep or standby mode, device needs 35 s typ. to be ready. no need for a delay for device ready. transition time at least 8.0 s, to differentiate between a static transition and p_spi communication immediate transition. however, the err pin has weak driver and an 8.0 s stabilization time is required. when the device is switched between normal and listen only mode to check the fail flag, a delay of 8.0 s is needed.
analog integrated circuit device data freescale semiconductor 29 33902 packaging package dimensions packaging package dimensions for the most current package revision, visit www.freescale.com and perform a keyword search using the 98asb42565b listed below. ef-pin (pb-free) 98asb42565b issue h
analog integrated circuit device data 30 freescale semiconductor 33902 revision history revision history revision date description of changes 3.0 8/2009 ? initial release
how to reach us: home page: www.freescale.com web support: http://www.freescale.com/support usa/europe or locations not listed: freescale semiconductor, inc. technical information center, el516 2100 east elliot road tempe, arizona 85284 1-800-521-6274 or +1-480-768-2130 www.freescale.com/support europe, middle east, and africa: freescale halbleiter deutschland gmbh technical information center schatzbogen 7 81829 muenchen, germany +44 1296 380 456 (english) +46 8 52200080 (english) +49 89 92103 559 (german) +33 1 69 35 48 48 (french) www.freescale.com/support japan: freescale semiconductor japan ltd. headquarters arco tower 15f 1-8-1, shimo-meguro, meguro-ku, tokyo 153-0064 japan 0120 191014 or +81 3 5437 9125 support.japan@freescale.com asia/pacific: freescale semiconductor china ltd. exchange building 23f no. 118 jianguo road chaoyang district beijing 100022 china +86 10 5879 8000 support.asia@freescale.com for literature requests only: freescale semiconductor literature distribution center p.o. box 5405 denver, colorado 80217 1-800-441-2447 or +1-303-675-2140 fax: +1-303-675-2150 ldcforfreescalesemiconductor@hibbertgroup.com freescale? and the freescale logo are trademarks of freescale semiconductor, inc. all other product or service names are the property of their respective owners. ? freescale semiconductor, inc. 2009. all rights reserved. MC33902 rev. 3.0 8/2009 information in this document is provided solely to enable system and software implementers to use freescale semiconductor products. there are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document. freescale semiconductor reserves the right to make changes without further notice to any products herein. freescale semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does freescale semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. ?typical? parameters that may be provided in freescale semiconductor data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including ?typicals?, must be validated for each customer application by customer?s technical ex perts. freescale semiconductor does not convey any license under its patent rights nor the rights of others. freescale semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the freescale semiconductor product could create a situation where personal injury or death may occur. should buyer purchase or use freescale semiconductor products for any such unintended or unauthorized application, buyer shall indemnify and hold freescale semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that freescale semiconductor was negligent regarding the design or manufacture of the part.

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